System-on-Module datasheet

Features

Overview

The Coral System-on-Module (SoM) is a fully-integrated system that helps you build embedded systems that demand fast machine learning (ML) inferencing. It contains NXP's iMX 8M system-on-chip (SoC), eMMC memory, LPDDR4 RAM, Wi-Fi, and Bluetooth, but its unique power comes from Google's Edge TPU coprocessor.

The Edge TPU is a small ASIC designed by Google that provides high performance ML inferencing with a low power cost. For example, it can execute state-of-the-art mobile vision models such as MobileNet v2 at almost 400 FPS, in a power efficient manner. This on-device processing reduces latency, increases data privacy, and removes the need for a high-bandwidth connection used to perform ML inferencing in the cloud.

Key benefits of the SoM:

  • High-speed and low-power ML inferencing (4 TOPS @2 W)
  • A complete Linux system (running Mendel, a Debian derivative)
  • Small footprint (40 x 48 mm)

The SoM is also included in the Coral Dev Board, which is a single-board computer that enables fast prototyping and evaluation of the standalone SoM.

System components

Block diagrams

Figures 1 and 2 illustrate the core components on the SoM and SoC.

Figure 1. Block diagram of the SoM components
Figure 2. Block diagram of iMX 8M SoC components, provided by NXP (some I/O signals on the SoC are consumed on the SoM, so refer to table 1 for availability)

Mechanical dimensions

SoM mechanical dimensions
Measurement Value
Size 48 x 40 x 5.11 mm
Weight 13 g

Figure 3 illustrates all of the SoM's dimensions. For a top-down view of the baseboard connector locations and component height restrictions, see the Baseboard developer guide.

Figure 3. SoM dimensions (in millimeters)

System power

The SoM requires 5 V as power input (at VSYS_5V). The SoM then generates the local voltage rails for all SoM components through on-board PMICs.

SoM power requirements
Power input Voltage
Main power supply (VSYS_5V) 5 V ± 5%
Caution: Do not connect the 1.8/3.3 V power output pins to any high current devices or you might brownout the system. These power lines are shared with internal SoM circuits, so there is no safe limit for a high current device, but you can safely use them for low current tasks such as for a level shifter or pull-up/down.
Caution: Do not connect any of the 3.3 V I/O pins to a device that draws more than ~ 82 mA of power or you will brownout the system.

Power signals

Even though there are multiple power signals defined in the board-to-board connectors, only the VSYS_5V and ground connections are required. All others are optional.

Note: Make sure to route all the VSYS_5V and GND pins, and add decoupling (bypass) capacitors between VSYS_5V and GND near the mating connector pins.

Power consumption

Caution: You must provide a cooling solution to ensure the SoM surface maintains an operational temperature as specified in the Environmental reliability section. Unlike the Coral Dev Board, the standalone SoM does not include a cooling solution (the SoM components are covered only with an EMI shield).

The power consumption numbers listed in this section are based on a high performance test that includes the following:

  • GPU: 3D rendering
  • CPU: 2 of 4 cores 100% loaded
  • Active Wi-Fi download
  • 7" HDMI display on
  • DDR: 800 MHz
  • Edge TPU running MobileNet V1 at 500 MHz
  • Fan intermittently on

Table 5 lists the power draw measurements during different operational tests both for both the SoM, and for the Dev Board baseboard and SoM working together.

SoM power draw measurements
Operational test SoM power System power (SoM + Dev Board baseboard)*
Idle 2.6 W 4.0 W
Idle with HDMI display on 3.0 W 4.3 W
High performance 6.2 W 8.5 W

* Tested with Coral Dev Board—performance on your custom baseboard may vary

During the high performance test, the top power-consuming components (top heat sources) are as indicated in figure 4.

Figure 4. Power draw and ordinate locations (in millimeters) of top power components on the SoM during high performance test

Boot mode

Use the BOOT_MODE[1:0] pins to configure the SoM boot mode setting as indicated in the following tables.

Boot mode pin signals
Name Type Connector Pins Voltage Description
BOOT_MODE0 Input J1312 64 3.3 V SoC BOOT_MODE0 signal (can be set by switch or pin-strap on baseboard)
BOOT_MODE1 Input J1312 62 3.3 V SoC BOOT_MODE1 signal (can be set by switch or pin-strap on baseboard)
Boot mode pin settings
BOOT_MODE[1:0] bits Boot type
00 Boot from fuses (default behavior)
01 Serial downloader
10 Internal boot
11 Reserved

The boot configuration is specified by the iMX 8M SoC, so for more details, refer to the iMX 8M SoC documentation.

Note: If BOOT_MODE[1:0] is "10" (internal boot), then GPIO pins SAI1_RX[7:0] and SAI1_TX[7:0] are used to enable boot configuration overrides (such as whether to boot from eMMC or SD card) by latching them to the BOOT_CFG[15:0] bits in the SoC. For further details, such as information about GPIO boot overrides and boot fuses, see the iMX 8M SoC documentation.

Peripheral interfaces

The following interfaces are available from the SoM, through the three 100-pin board-to-board connectors.

This section is organized based on the default pin functions when running the Mendel operating system. For information about alternative pin functions you may enable with your own device tree overlay, see the iMX 8M SoC documentation.

Note: All I/O pins have a 90 k pull-down resistor in the SoC that are used by default during bootup, which you can reconfigure with a device tree overlay after bootup. However, some pins (such as I2C, some SAI, and some SD2 pins) also have pull-up resistors inside the SoM, as noted in the following tables, which you cannot reconfigure with a device tree overlay.
Caution: Do not connect any of the 3.3 V I/O pins to a device that draws more than ~ 82 mA of power or you will brownout the system.

MIPI camera (CSI)

There are two channels for MIPI camera serial interface (CSI-2), each with four lanes and a maximum bit rate of 1.5 Gbps.

CSI channel 1 pins
Name Type Connector Pins Voltage Description
MIPI_CSI1_CLK_P/N Input J1311 18/16 0.2-1.2 V MIPI CSI1 clock (positive/negative)
MIPI_CSI1_D0_P/N Input J1311 12/10 0.2-1.2 V MIPI CSI1 data (positive/negative)
MIPI_CSI1_D1_P/N Input J1311 23/21 0.2-1.2 V MIPI CSI1 data (positive/negative)
MIPI_CSI1_D2_P/N Input J1311 6/4 0.2-1.2 V MIPI CSI1 data (positive/negative)
MIPI_CSI1_D3_P/N Input J1311 29/27 0.2-1.2 V MIPI CSI1 data (positive/negative)
CSI channel 2 pins
Name Type Connector Pins Voltage Description
MIPI_CSI2_CLK_P/N Input J1311 36/34 0.2-1.2 V MIPI CSI2 clock (positive/negative)
MIPI_CSI2_D0_P/N Input J1311 35/33 0.2-1.2 V MIPI CSI2 data (positive/negative)
MIPI_CSI2_D1_P/N Input J1311 30/28 0.2-1.2 V MIPI CSI2 data (positive/negative)
MIPI_CSI2_D2_P/N Input J1311 24/22 0.2-1.2 V MIPI CSI2 data (positive/negative)
MIPI_CSI2_D3_P/N Input J1311 41/39 0.2-1.2 V MIPI CSI2 data (positive/negative)

MIPI display (DSI)

The four-lane MIPI display serial interface (DSI) offers the following features:

  • Resolution up to 1920 x 1080 at 60 Hz
  • LCDIF display controller
  • Maximum bit rate of 1.5 Gbps
DSI pins
Name Type Connector Pins Voltage Description
MIPI_DSI1_CLK_P/N Output J1311 59/57 0.2-1.2 V MIPI DSI clock (positive/negative)
MIPI_DSI1_D0_P/N Output J1311 47/45 0.2-1.2 V MIPI DSI data (positive/negative)
MIPI_DSI1_D1_P/N Output J1311 54/52 0.2-1.2 V MIPI DSI data (positive/negative)
MIPI_DSI1_D2_P/N Output J1311 42/30 0.2-1.2 V MIPI DSI data (positive/negative)
MIPI_DSI1_D3_P/N Output J1311 48/46 0.2-1.2 V MIPI DSI data (positive/negative)

HDMI

The High-Definition Multimedia Interface (HDMI) connection provides the following features:

  • HDMI 2.0a supporting one display up to 1080p
  • Upscale and downscale between 4K and HD video (requires full system resources)
  • 20+ Audio interfaces 32-bit @ 384 kHz fs, with Time Division Multiplexing (TDM) support
  • SPDIF input and output
  • Audio Return Channel (ARC) on HDMI
HDMI pins
Name Type Connector Pins Voltage Description
HDMI_REFCLKP/N Output J1310 58/60 3.3 V HDMI reference clock (27 Mhz) (positive/negative)
HDMI_CLKP/N Output J1312 68/70 3.3 V HDMI clock (positive/negative)
HDMI_TX0_P/N Output J1312 75/73 3.3 V HDMI transmit (positive/negative)
HDMI_TX1_P/N Output J1312 79/81 3.3 V HDMI transmit (positive/negative)
HDMI_TX2_P/N Output J1312 76/74 3.3 V HDMI transmit (positive/negative)
HDMI_AUX_P/N Output J1312 82/80 3.3 V HDMI AUX (positive/negative)
HDMI_HPD Output J1312 89 3.3 V HDMI Hot Plug Detect
HDMI_DDC_SDA Output J1312 85 3.3 V HDMI Display Data Channel data
HDMI_DDC_SCL Output J1312 87 3.3 V HDMI Display Data Channel clock
HDMI_CEC Output J1312 91 3.3 V HDMI Consumer Electronic Control

Ethernet

The Ethernet Media Access Controller (MAC) supports 10/100/1000 Mbps Ethernet/IEEE 802.3 networks with reduced gigabit media-independent interface (RGMII). Requires an Ethernet PHY on the baseboard.

PCIe

The SoC includes PCIE1 and PCIE2 lines that are routed to the baseboard connectors, but you should not need to connect these and you should not remap these with your own device tree because both are used on the SoM for Wi-Fi (PCIE1) and the Edge TPU (PCIE2).

USB

There are two USB controllers and corresponding PHYs on the SoM. Each USB instance contains USB 3.0 (USB 3.1 Gen 1) core, which can operate in both USB 3.0 and 2.0 mode.

USB channel 1 pins
Name Type Connector Pins Voltage Description
USB1_DP/N I/O J1311 51/53 3.3 V USB 2.0 (positive/negative)
USB1_TXP/N Output J1311 58/60 1.8 V USB 3.0 transmit (positive/negative)
USB1_RXP/N Input J1311 64/66 1.8 V USB 3.0 receive (positive/negative)
USB1_VBUS Input J1311 82/84 5 V VBUS detect (same at both pins)
USB1_ID Input J1311 76 3.3 V USB ID
USB channel 2 pins
Name Type Connector Pins Voltage Description
USB2_DP/N I/O J1311 63/65 3.3 V USB 2.0 (positive/negative)
USB2_TXP/N Output J1311 69/71 1.8 V USB 3.0 transmit (positive/negative)
USB2_RXP/N Input J1311 70/72 1.8 V USB 3.0 receive (positive/negative)
USB2_VBUS Input J1311 75/77 5 V VBUS detect (same at both pins)
USB2_ID Input J1311 88 3.3 V USB ID

Digital audio (SAI)

The SAI module provides a synchronous audio interface (SAI) that supports full duplex serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces.

Note: If booting the SoM in eFUSE mode (default behavior), all SAI pins are available during boot. However, when using the other boot modes, pins SAI1_RX[7:0] and SAI1_TX[7:0] are used to enable boot configuration overrides by latching them to the BOOT_CFG[15:0] bits in the SoC—that is, only until boot completes. The SoM uses internal pin strap (pull-up and pull-down) resistors to select the different boot configuration, so you should be careful if you add any pull-up/down resistors for these pins on your baseboard. For details, see the iMX 8M SoC documentation.
SAI 2 signals
Name Type Connector Pins Voltage Description
SAI2_TXD Output J1312 14 3.3 V Transmit channel
SAI2_RXD Input J1312 20 3.3 V Receive channel
SAI2_TXC Output J1312 18 3.3 V Transmit bit clock
SAI2_TXFS Output J1312 16 3.3 V Transmit frame sync
SAI2_MCLK I/O J1312 12 3.3 V Audio master clock
SAI2_RXFS Input J1312 24 3.3 V Receive frame sync
SAI2_RXC Input J1312 23 3.3 V Receive bit clock

Sony/Philips audio (SPDIF)

Sony/Philips Digital Interface (SPDIF) is a standard audio file transfer format that supports Transmitter and Receiver functionality. Refer to NXP iMX 8M documentation for additional details.

SPDIF pin signals
Name Type Connector Pins Voltage Description
SPDIF_EXT_CLK Output J1311 92 3.3 V External clock signal
SPDIF_TX Output J1311 96 3.3 V Transmit data channel
SPDIF_RX Input J1311 98 3.3 V Receive data channel

Micro-SD card

An Ultra Secure Digital Host Controller (uSDHC) module provides the interface between the host and SD/SDIO/MMC cards, with the following features:

  • SD/SDIO standard, up to version 3.0
  • MMC standard, up to version 5.0
  • 3.3 V operation only
  • 1- and 4-bit SD/SDIO/MMC modes

JTAG debugging

5-pin JTAG debugging with a Secure JTAG Controller (SJC) for secure debugging.

JTAG pin signals
Name Type Connector Pins Voltage Description
JTAG_TMS Output J1312 59 3.3 V Test mode select
JTAG_TDI Input J1312 61 3.3 V Test data in
JTAG_TDO Output J1312 57 3.3 V Test data out
JTAG_TCK Output J1312 53 3.3 V Test clock
JTAG_nTRST Input J1312 55 3.3 V Test reset

I2C

Two I2C bus interfaces are available.

Note: The SoC also includes I2C1 and I2C4 lines, but these are used by the SoM for power management and wireless controls, so you should not remap these with your own device tree.

UART

Two UART v2 modules are available with the following features:

  • 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd, or none).
  • Programmable baud rates up to 4 Mbps.
  • 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud.
Note: By default, the Mendel operating system configures UART1 for use with the the serial console.

The SoC also includes UART2 and UART4 lines, but these are used by the SoM for Bluetooth, so you should not remap these with your own device tree.

SPI

Two full-duplex eSPI interfaces are available, with data rates up to 52 Mbit/s and two chip select lines.

SPI channel 1 pin signals
Name Type Connector Pins Voltage Description
ECSPI1_MISO Input J1312 5 3.3 V Master input
ECSPI1_MOSI Output J1312 7 3.3 V Master output
ECSPI1_SCLK Output J1312 4 3.3 V Serial clock
ECSPI1_SS0 Output J1312 8 3.3 V Chip select
ECSPI1_SS1 Output J1310 6 3.3 V Chip select
SPI channel 2 pin signals
Name Type Connector Pins Voltage Description
ECSPI2_MISO Input J1312 3 3.3 V Master input
ECSPI2_MOSI Output J1312 6 3.3 V Master output
ECSPI2_SCLK Output J1312 2 3.3 V Serial clock
ECSPI2_SS0 Output J1312 1 3.3 V Chip select
ECSPI2_SS1 Output J1310 4 3.3 V Chip select

GPIO

The following pins are configured for general purpose input/output, by default. Additionally, you can reconfigure other pins (SAI, SPDIF, SDIO, I2C, UART, SPI, and PWM) to behave as GPIO, using a device tree overlay.

PWM

There are four PWM output pins available with 16-bit resolution and 4x16 data FIFO.

PWM pin signals
Name Type Connector Pins Voltage Description
PWM1 (GPIO1_IO01) Output J1312 88 3.3 V PWM or GPIO
PWM2 (GPIO1_IO013) Output J1312 90 3.3 V PWM or GPIO
PWM3 (GPIO1_IO014) Output J1312 92 3.3 V PWM or GPIO
PWM4 (SAI3_MCLK) Output J1312 11 3.3 V PWM or GPIO

Wi-Fi and Bluetooth

The SoM includes the Murata LBEE5U91CQ module, which provides Wi-Fi (IEEE 802.11 a/b/g/n/ac WLAN, 2.4/5 GHz) and Bluetooth 4.2 (with Bluetooth Low Energy support), using wireless antennas integrated into the board.

Baseboard developer guide

This section provides details to help you integrate the Coral SoM into your own baseboard (carrier board) hardware.

Reference design

If you'd like to see a reference baseboard design that uses the System-on-Module, download the following schematic and layout files for the Coral Dev Board.

Dev Board schematics, layout, and 3D files
FileDescription
Coral-Dev-Board-baseboard-schematic.pdf Baseboard schematic in PDF
Coral-Dev-Board-baseboard-schematic-Altium.zip Baseboard schematic files in Altium format
Coral-Dev-Board-baseboard-layout-Allegro.brd Baseboard CAD layout in BRD format
Coral-Dev-Board.STEP Dev Board (baseboard and SoM) 3D CAD file in STEP format
Coral-SoM.STEP SoM-only 3D CAD file in STEP format

Baseboard connectors

The SoM connects to the host baseboard with three 100-pin connectors.

SoM and baseboard connectors
SoM Baseboard
3x 100-position plug
Hirose Electric DF40C-100DP-0.4V(51)
3x 100-position receptacle
Hirose Electric DF40HC(3.0)-100DS-0.4V(51)

The location of each connector plug on the SoM is illustrated in figure 3, and the corresponding position for each receptacle on your baseboard is illustrated in figure 5.

Connectors, keepouts, and component max heights

Figure 5 illustrates the area of your baseboard where the SoM connects. The measurements are relative to the standoff in the bottom-left corner, indicating the position for the three board-to-board (B2B) connectors (Hirose DF40C-100DP-0.4V), two standoffs, and the following component regions:

  1. Antenna keepout: Place no components and no copper in this region. This area of your baseboard is directly below the SoM's Wi-Fi and Bluetooth antennas, so it must be kept clear of any metals to ensure strong radio signals.
  2. Max height of baseboard components in this region is 2.8mm.
  3. Max height of baseboard components in this region is 1.5mm.

Additionally, figure 5 indicates the location of pin 1 on your baseboard connectors. To see all the pin assignments, refer to the pinout schematic.

Figure 5. Top view of baseboard connectors and component restrictions (measured in millimeters)

Trace impedance recommendations

The following table lists the recommended impedance for high-speed signals on the baseboard.

MIPI trace length compensation

MIPI signals for the CSI/DSI interfaces are high-speed signals that require the total etched trace lengths for each line within a group (the paired clock lanes and four data lanes) be equal to each other. Due to space constraints on the SoM, the MIPI signal traces lengths currently are not equal (as indicated in the following tables). You must incorporate the length difference on your baseboard traces such that the trace lengths for each MIPI group match each other.

Other recommendations

  • Make sure to route all the VSYS_5V and GND pins, and add decoupling (bypass) capacitors between VSYS_5V and GND near the mating connector pins.
  • When placing a pull-up or pull-down resistor on some of the SoM signals, such as I/O pins (especially SAI1_TXD[7:0] and SAI1_RXD[7:0]), review the signal description for each peripheral interface, because some of them already have pull-up/down resistor in the SoM for initialization purposes.
Caution: You must provide a cooling solution to ensure the SoM surface maintains an operational temperature as specified in the Environmental reliability section. You can use the SoM's threaded standoffs (indicated in figure 3) to mount a passive or active cooling solution.

Pinout schematic

Caution: The signal directions in figure 6 are not all accurate. Instead refer to the "type" of each pin in the tables from the Peripheral interfaces section.

Environmental reliability

Certifications

Document revisions

History of changes to this document
Version Changes
1.6 (April 2020) Add detail about SAI5 pins that are pin-strapped in the SoM.
1.5 (February 2020) Clarify and enhance documentation of SAI, power and reset pin signals.
Add information about PWRON_B pin.
1.4 (January 2020) Fix USB2_RXP/N pin position.
1.3 (December 2019) Fix HDMI_TX1 pin positions.
1.2 (August 2019) Add PDF download of this datasheet and the Dev Board baseboard schematic.
1.1 (July 2019) Remove wireless antenna connector details.
1.0 (June 2019) Initial release.